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Page 3 Architectures

General Information

Document Type:MOD
Posted Date:Oct 18, 2017
Category: Research and Development
Set Aside:N/A

Contracting Office Address

675 North Randolph Street Arlington, VA 22203

Description

Amendment 02: The purpose of this amendment is to correct a typographical error in the abstract details on page 41. See the attached conformed BAA with changes highlighted in yellow. Amendment 01: The purpose of this amendment is to make administrative changes as highlighted in yellow in the attached. Original Synopsis Below: DARPA is soliciting innovative research proposals in the area of novel computing architectures. The Page 3: Architectures thrust of the Electronics Resurgence Initiative (ERI) seeks to demonstrate heterogeneous computing systems that provide the performance advantages of specialized processors, while maintaining the programmability of general purpose processors. The goal of the Software Defined Hardware (SDH) program is to build runtime-reconfigurable hardware and software that enables near ASIC performance without sacrificing programmability for data-intensive algorithms. SDH will create a hardware/software system that allows data-intensive algorithms to run at near ASIC efficiency without the cost, development time or single application limitations associated with ASIC development. The overall goal of the Domain-specific System on Chip (DSSoC) program is to develop a heterogeneous SoC comprised of many cores that mix general-purpose processors, special-purpose processors, hardware accelerators, memory, and input/output (I/O). DSSoC seeks to enable rapid development of multi-application systems through a single programmable device. **Updated NAICS Code only.**

Original Point of Contact

POC BAA Coordinator,

Place of Performance

Link: FBO.gov Permalink
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